Various types of logic analyzers or evaluation-type devices have been designed in the past. For example, U.S. Pat. No. 4,334,305 to H. Thinschmidt et al. concerns an error evaluation test arrangement for a multi-micro-computer system. The arrangement is generally made up of a bus for interconnection to each system to be evaluated. A series of three logic evaluation/control devices are connected to the bus for enabling evaluation of the full bus width output of each computer system. One or more optic display devices are connected to each logic device. U.S. Pat. No. 4,425,643 to David D. Chapman et al. concerns a multi-speed logic analyzer. The analyzer is generally made up of two data input memory sections where each section is capable of receiving data at different clock rates. An I/O bus of the analyzer interconnects the input sections with the analyzer/control arrangement thereof. Each input section is provided with a data word trigger device that responds to one or more coded bits of an input for controlling the operation of the analyzer of the control/analyzer arrangement during operator use. U.S. Pat. No. 4,517,671 to J. D. Lewis discloses a visual display apparatus for analyzing the performance output of a computer. The apparatus is generally made up of a series of buffers for selectively interconnecting a computer to be analyzed. The apparatus is further provided with operator control logic, data input pattern recognizers, etc., so that the display will provide an analytic output desired. U.S. Pat. No. 4,636,941 to S. Suko concerns an analyzer for a microprocessor that needs to be evaluated. The analyzer is generally made up of a control microprocessor, a memory, a trigger comparison circuit and routine detection circuits for receiving bus output data from a microprocessor being evaluated and selectively coupled to the analyzer for evaluation. When the trigger comparison circuit detects a fault in the bus output data, the analyzer is stopped thereby rejecting the microprocessor. However, none of the aforediscussed references, whether taken alone or in any combination, remotely contemplated an improved multimode/multiconfigurable digital data evaluation system that preferably operates at a relatively high frequency and that can readily and quickly analyze a variety of multibit data word stream outputs of more than one type of digital data source means, e.g., main frame computer or smaller. Depending on the size of the digital data source means being evaluated by the improved system, more than one source means can be evaluated at the same time. At the same time the system in being of solid-state construction is of relatively small, lightweight modular construction so that it can readily be used in the field or laboratory. In other words, this highly versatile and improved DARP (digital dta evaluation) system of applicants, as will be described below, not only is highly versatile and multiconfigurable during use; but it is readily portable and thus can be easily transported to where the digital data source means or computer is that needs to be periodically evaluated so as to enable certification of its operational performance.